@INPROCEEDINGS{1301984,
author={Adi, W. and Soudan, B. and Kassab, N.},
booktitle={Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International Conference on},
title={A protection mechanism for intellectual property rights (IPR) in FPGA design environment},
year={2003},
volume={1},
pages={92-95 Vol.1},
keywords={VLSI;cryptography;field programmable gate arrays;industrial property;integrated circuit design;integrated circuit testing;logic design;logic testing;message authentication;protocols;FPGA design environment;FPGA hardware environment;IPR protection;VLSI designs;business agreement;design testing;field testing;hardware-supported design encryption;intellectual property rights protection mechanism;limited deployments;limited field deployment;secured authentication protocols;tester design details deciphering;Authentication;Educational institutions;Field programmable gate arrays;Hardware;Intellectual property;Manufacturing;Programming profession;Protection;Testing;Very large scale integration},
doi={10.1109/ICECS.2003.1301984},}