@ARTICLE{4014536,
author={Kirovski, D. and Yean-Yow Hwang and Potkonjak, M. and Cong, J.},
journal={Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on},
title={Protecting Combinational Logic Synthesis Solutions},
year={2006},
volume={25},
number={12},
pages={2687-2696},
keywords={combinational circuits;industrial property;logic CAD;logic design;watermarking;combinational logic synthesis;design reuse;design watermarking;intellectual-property protection;intellectual-property-business model;multilevel combinational synthesis;multilevel logic minimization;technology mapping;template matching;tool-specific information;user-specific information;Companies;Cryptography;Design optimization;Large scale integration;Logic design;Network synthesis;Protection;Protocols;Silicon;Watermarking;Intellectual property protection, logic synthesis, multilevel combinational synthesis, template matching, watermarking},
doi={10.1109/TCAD.2006.882490},
ISSN={0278-0070},}